1. Field of the Invention
The present invention relates to a bus data path control scheme. In particular, the present invention relates to a scheme in a data processing system by which subsystems of the data processing system, having different data widths, are capable of communicating with each other in a fast manner where a minimum amount of hardware is required for interfacing the subsystems.
2. Description of the Related Art
Known data processing systems may consist of a central processing unit and a plurality of subsystems. In particular, data processing systems may include a plurality of memory subsystems such as dynamic random access memories (dRAMs), video dynamic random access memories (video dRAMs) and other read only memories (ROMs). The data processing system may also include such subsystems as a disk controller, a cursor controller, a serial line controller and/or a plurality of other subsystem elements.
It is possible that not all of the subsystem elements of the data processing system will have the same data widths. For example, a disk controller in the system may be a 32 bit disk controller, that is it may have a data width of 32 bits. In contrast, a serial line controller in the system may be a 16 bit device. Similarly, memory devices in the system may be 16 or 32 bit devices.
It is sometimes necessary to transfer data from a device or subsystem having a first data width to a device or subsystem having a second data width where the two data widths are different.
Prior data processing systems have accommodated such transfers by using registers and multiplexers on the inputs and outputs of each of the subsystems. The multiplexers and registers permit a conversion of the data width of a device so as to make communications between devices having different data widths more uniform. Unfortunately, registers and multiplexers for the inputs and outputs of each of the subsystems constitute a considerable amount of hardware. In addition, signal processing through these multiplexers and registers introduces an undesirable amount of delay into the operation of the system.